The core of a modern high speed microprocessor system, as shown in FIG. 1, consists of number of subsystems such as the microprocessor (CPU 11), secondary cache controller 12 and the secondary cache memory 13. The communication between the subsystems is performed over the CPU bus 14. Highly integrated modern VLSI processes, allows the CPU 11 to include an on chip primary cache 15 and floating point unit (FPU 16). The CPU 11 may generally include additional units that are not essential to the subject matter of this invention and are therefore omitted for clarity from FIG. 1.
Synchronous operation of the various units in the microprocessor system is accomplished by means of the CLK signal. Each unit uses the CLK signal for sequencing the operation of internal sequential logic circuits such as synchronous state machines. Inside CPU 11, the CLK is generated by the clock generator circuit (CLKGEN) 17. In the past, a double frequency (2.times.) clock signal, CLK2, was used as a main system reference clock. The CLK2 reference signal comprised a series of pulse waveforms with twice the frequency of the CLK signal (F.sub.CLK2 =2*F.sub.CLK). FIG. 2 shows a typical prior art implementation of the CLKGEN circuit 17. The frequency of external CLK2 signal is divided by two by D-type flip-flop (TFF) 18 with its Q# output connected to its D input and buffered by a clock driver (CLKDRV) 19, creating the internal CLK signal with 50% duty-cycle, regardless of the duty-cycle of the external CLK2 signal. However, for modern microprocessor systems running at frequencies of 50 to 100 MHz CLK, the 2.times. clock frequency is 100 to 200 MHz. At these frequencies, designing the system distribution of the 2.times. clock is very complex, expensive and requires substantial skill in high frequency analog techniques. Moreover, at frequencies of 50 to 100 MHz, the 2 to 3 ns delay of the on-chip CLK driver constitutes a significant delay of 10 to 30% of the CLK period. These delays preclude the use of traditional means for CLK generation in modern microprocessors. A way to solve the problem is to use the 1.times. CLK signal as the system clock instead of the CLK2 signal. However, because of the need to have a 50% duty-cycle internal CLK signal with zero skew relative to the external clock signal, it is necessary to eliminate the delay of the internal clock driver 19. (To eliminate the confusion between the internal and the external clock signals, the external clock will be referred to as CLKTTL and the internal clock as CLK.)
One way to generate CLK with a 50% duty-cycle and zero skew between the external CLKTTL and the internal CLK signals is by using a phase-locked-loop (PLL), as shown in the block diagram of FIG. 3. The use of a sequential phase-frequency detector (PFD) 20 and Charge-Pump (CP) 21 in the PLL results in zero skew between the CLK and CLKTTL signals. The 50% duty-cycle is realized by using voltage controlled oscillator (VCO) 23 oscillating at twice the CLKTTL frequency and then dividing its frequency by two using frequency divider network 24 which is similar to divider network TFF 18 of FIG. 2. Further details about charge pump PLLs may be found in Gardner, F., Phaselock Techniques (John Wiley, 1979).
However, implementation of a PLL circuit using a digital VLSI process and operation of a PLL on the same substrate with noisy digital (on-off) circuits such as microprocessors, introduces further complications. The PLL analog circuit performance and reliability is adversely affected by this digital noise. The degree of sensitivity to noise is strongly affected by manufacturing process variations and by operating conditions. On the other hand, the digital parts of the microprocessor system are more robust than the analog parts of the PLL, showing greater immunity to process and environmental variations. Hence, reliable operation of PLL circuit on the same substrate with digital microprocessor, is very difficult to guarantee.
As can be seen from FIG. 3, the PLL's low pass filter (LPF) 22 uses a resistor R2 which is required to assure closed loop stability of the PLL. Unfortunately, modern digital VLSI processes lack the ability to provide reasonably valued resistors unless a well type resistor is used for R2. However, well-type resistors have high parasitic capacitance to the silicon substrate. In digital chips, like a microprocessor, this leads to coupling of the substrate noise to the sensitive LPF 22 output node V.sub.CNTL. Noise on node V.sub.CNTL has a deleterious effect on operation of the PLL because it directly modulates the phase and frequency of the CLK signal. Hence, the zero skew locking of the PLL is subject to significant errors due to the substrate noise coupling.
In addition, it can be shown that the oscillation frequency of the VCO is highly sensitive to the power supply voltage noise. When the digital part of the microprocessor is operating, a very high noise level is generated on the internal power supplies of the chip due to on-off transients which significantly modulates the phase of the CLK signal. Consequently, the zero skew locking of the PLL can not be guaranteed due to noisy power supplies. One may suggest a separate set of filtered power supplies, solely for the PLL circuit on the microprocessor chip. However, use of isolated power supplies raises serious electro-static-discharge (ESD) reliability problems in addition to requiring additional filtering components external to the chip.
Therefore, it is undesirable to implement a mass production PLL circuit, residing on same substrate with the noisy digital circuits, which must be guaranteed to operate reliably but was manufactured by using a standard digital VLSI process.